1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device.
2. Description of the Related Art
As the insulating film in the semiconductor device, the silicon oxide film has been being used for various purposes and its application range includes the Trench Isolation, the interconnection interlayer film and the like. However, in recent years, accompanying the miniaturization of the semiconductor device, it has become demanded that the deposition thereof gives still better performance for filling up the pattern and the chemical mechanical polishing (referred to as the CMP (Chemical Mechanical Polishing) polishing hereinafter) that is the fabrication technique therefor has a higher controllability and uniformity.
As the silicon oxide film of excellent filling-up capability, a high density plasma CVD (Chemical Vapor Deposition) oxide film (referred to as the HDP oxide film hereinafter) described in Japanese Patent Application Laid-open No. 079423/1998 and the like has been currently in wide use.
The deposition of the film by the high density plasma CVD method is a technique in which the deposition of the film and the sputtering are simultaneously carried out so as to bury the difference in level of the uneven film surface. This technique excels in filling-up capability but leaves the film in characteristic form having, on the top of each upper level section thereof, a projection shaped like the mesa, the peaked roof or the cone (referred to as a projection hereinafter).
For the CMP polishing of the oxide film, the use of alumina, zirconia or silica slurry has been examined but the silica slurry with a selection ratio of the polishing rate of 4 or so (silicon oxide film/silicon nitride film) is generally utilized. The silicon slurry, however, allows the nitride film that acts as a stopper film at the time of polishing to be polished so that a slurry having a higher selection ratio of the polishing rate and a higher controllability than the silica slurry has been called for. On the other hand, although alumina, zirconia and silica slurry have the disadvantage of low selection ratio of the polishing rate, their grain sizes are as small as 0.2 μm and their grains make no aggregation, thus, causing few polishing scars even when projections are present as on the surface of the HDP oxide film.
As the CMP polishing of good controllability, the CMP polishing described in Japanese Patent Application Laid-open No. 085373/2001, wherein a polishing agent containing cerium oxide (ceria) as grains (referred to as a ceria slurry hereinafter) is used has been attracting special interests.
The strong points of the CMP polishing with the ceria slurry are its high selection ratio of the polishing rate (silicon oxide film/silicon nitride film) of 20 to 60 or so which is much higher than that of the conventional silica slurry of 4 or so and its excellent planarizing performance. On the other hand, the grain size of the ceria slurry is greater than that of the silica slurry (silica slurry: the average 0.1 μm, ceria slurry: the average 0.2 μm, the maximum 1.1 μm), and, furthermore, on mixing the ceria grain agent and the additive, large particles (2 to several tens μm) are liable to appear due to aggregation. When some of grains the slurry contains, as in the ceria slurry, have grain sizes exceeding 1 μm, even if the CMP polishing is carried out immediately after the mixing, the polishing scars are produced in the presence of the projections. Moreover, the appearance of large particles through aggregation of the grains tends to increase the dimensions of the polishing scars, which is clearly a weak point for this polishing.
FIG. 7 is a series of schematic cross-sectional views of a semiconductor substrate illustrating, in sequence, the steps of a manufacturing method, taking the case of the steps of forming a trench isolation, and, herein, an example of a conventional method of applying a CMP polishing treatment with a ceria slurry to a semiconductor substrate buried under a HDP oxide film is shown.
First, as shown in FIG. 7(a), on a semiconductor substrate 25, a thermal oxide film 26 was grown to a thickness of 10 nm, and thereon a nitride film 27 was grown to a thickness of 140 nm or so by the low pressure CVD method and, then, a KrF resist 28 was formed on an element formation region by means of KrF excimer lithography.
Next, as shown in FIG. 7(b), using the KrF resist as a mask, portions of the nitride film 27 and the thermal oxide film 26 lying on the element isolation regions were removed by plasma etching so as to make the thermal oxide film 26 and the nitride film 27a remain on the element formation region selectively. After that, the KrF resist 28 was removed.
Next, as shown In FIG. 7(c), using the nitride film 27a as a mask, plasma etching was applied thereto to form trenches with a depth of 250 nm in the element isolation regions of the semiconductor substrate 25. The nitride film 27a was, hereat, etched by 40 nm to a thickness of 100 nm.
Next, as shown in FIG. 7(d), after conducting a cleaning treatment such as an acid cleaning, a HDP oxide film 29 was grown by the high density plasma CVD method to a thickness of 400 nm so as to fill up the trench sections. The HDP oxide film 29, hereat, took the shape of a long tail in the periphery of the element formation region.
The tail of the HDP oxide film 29 made an angle of 56° to the surface of the semiconductor substrate. Further, the HDP oxide film 29 over the element formation region became trapezoidal when the width of the element formation region was large. When the width of the region was less than 540 nm (=2×400/tan 56°), however, the upper side of the trapezoid disappeared and the HDP oxide film formed a projection in the shape of a peaked roof or a cone whose angle of the apex of the cross-sectional isosceles triangle was 68°.
After that, as shown in FIG. 7(e), using the nitride film 27a as a polishing stopper, the HDP oxide film 29 on the element formation region was removed by the CMP polishing with a ceria slurry and the nitride film 27a was exposed.
The ceria slurry was hereat prepared by mixing a ceria grain agent HS-8005 and an additive HS-8102GP (made by Hitachi Chemical Co. Ltd.,) in the proportion of 1:2, and a CMP apparatus MIRRA 3400 (made by Applied Materials Inc.) and a polishing pad IC 1000 (made by Rodel Nitta Company) were utilized, but, obviously, they were not limited to these particular ones. As for the detection of the end point for the CMP polishing, the optical method was hereat employed.
While the ceria slurry had the disadvantage that polishing scars were liable to be produced as described above, its polishing rate for the nitride film was as one twentieth to one sixtieth or so as fast as its polishing rate for the oxide film and, therefore, the amount of polishing the nitride film received did not exceed 5 nm, and the polishing could be certainly stopped at the nitride film, indicating a high controllability this slurry provided.
Nevertheless, on the minute element formation regions with a width of 540 nm or less, there were observed numerous polishing scars which looked like scooped marks. It was considered that, changing into large particles, grains in the ceria slurry came into collisions with the projections on the minute element formation regions and made the projection tip(s) or itself broken or made the projection ridge(s) crumble, which brought about the polishing scars. Moreover, since these scars were made in the element formation regions, their adverse effect on the element operations were substantial and directly caused the lowering of the yield.
Next, as shown in FIG. 7(f), the nitride film 27a was removed by wet etching with phosphoric acid, and thereby the formation of the trench isolation was accomplished. Typically, more than 400 polishing scars like scooped marks (per 8-inch substrate) were observed on the minute element formation regions.
When a deposition of a film of anisotropic growth with a good filling-up capability, like the high density plasma CVD, is applied onto a basic substance having a difference in level on the surface, a projection appears on the top of each upper level section thereof.
Even with the CMP being applied to a state where the projection is formed, no problem arises when grains in a slurry are small. However, once some of grains form large particles, there arises a problem of breaking the projections and producing polishing scars.
In recent years, accompanying the miniaturization of the semiconductor device, the improvement of the filling-up capability and the increase in polishing accuracy have been simultaneously demanded. To meet these demands, it is essential to develop a novel technique in which both of the deposition by the high density plasma CVD methods which excels in filling-up capability and the CMP polishing with a ceria slurry which tends to produce polishing scars, with grains changing into large particles, but provides a high selection ratio of the polishing rate between the oxide film and the nitride film are employed but the production of the polishing scars is successfully suppressed.